1. Field of the Invention
The present invention relates to a circuit which generates a clock signal. Further, the present invention also relates to a semiconductor device mounted with such a circuit which generates a clock signal.
2. Description of the Related Art
In recent years, semiconductor devices (also referred to as RFID tags, wireless tags, ID tags, or RF tags) in which an ultrasmall IC chip and an antenna for radio communication are combined have been in the limelight. Such semiconductor devices enable non-contact transmitting and receiving of data (e.g. writing or reading out data) by transmitting and receiving communication signals to and from a transmitting/receiving circuit or the like using a radio communication device (an apparatus capable of radio communication: e.g. a reader/writer, a mobile phone, or a personal computer).
As an application field of semiconductor devices which transmit and receive data by radio signals, merchandise management in the distribution industry can be given, for example. Merchandise management using bar codes and the like is the mainstream at present; however, when there is an interrupting object, data cannot be read in some cases because bar codes are read optically. On the other hand, when data is transmitted and received without contact and with the use of a radio communication device, data of the semiconductor device is read wirelessly; thus, even when there is an interrupting object, the data can be read if radio communication signals pass through the interrupting object. Therefore, improvement in efficiency, cost reduction, and the like of merchandise management are expected. Further, a wide range of applications including passenger tickets, airplane tickets, and automatic payment of tolls is expected. Such a system that identifies and manages people or objects with a small semiconductor device which transmits and receives data by radio communication is called RFID (radio frequency identification), and has attracted attention as fundamental technology of the IT society (for example, see Reference 1: Japanese Published Patent Application No. H11-225091).
In transmitting and receiving signals between a radio communication device and a semiconductor device, it is possible to use different clock signals between the radio communication device and the semiconductor device. When different clock signals are used, however, data that is output from each of the devices corresponds to a clock of each device; therefore, when a fall of a reception signal which is output from the radio communication device and a rise of a clock in the semiconductor device are in synchronization with each other, there occurs a change in the duty ratio of the clock of the semiconductor device by a next fall of the reception signal; thus, set-up time and hold time of the signal are not kept constant, unfortunately.
As a circuit which generates clock signals, a PLL circuit can be given. A PLL circuit can control an oscillation frequency using a voltage regulating oscillator circuit (VCO). When a clock signal generation circuit is used for a passive semiconductor device or the like using a power supply at an external portion, a power-thrifty clock signal generation circuit without a VOC circuit or the like is required; however, when a power-thrifty clock signal generation circuit is used, it is difficult to generate a clock signal with a constant frequency due to the low power consumption.
In this specification, a change of a signal from low potential to high potential is referred to as a “rise.” Further, a change in a signal from high potential to low potential is referred as a “fall.”
Furthermore, in this specification, a point of change in potential at a rise or a fall is referred to as an “edge.”
A conventional method for generating a clock signal is described here. In a period of a synchronization signal which has a regular cycle and has been transmitted from an external circuit such as a radio communication device to a semiconductor device, the number of edges of a reference clock signal that has been output from a reference clock signal generation circuit such as a ring oscillator is counted by a counter circuit or the like, and a clock signal is generated on the basis of a value obtained by dividing a count value by an appropriate value for obtaining the clock signal with a given pulse number using a frequency division circuit or the like. At this time, a remainder obtained by dividing the count value by the appropriate value becomes a period in which a clock signal is not generated, and in each clock signal, unfortunately, a first half of cycles and a latter half of cycles have low periods of different lengths depending on a count value.
Here, one cycle means a period from an N-th (N is a natural number) fall to a subsequent (N+1)-th fall in a synchronization signal when an initial state is a high state.
In this specification, a high state designates a state of a signal rise, and a low state designates a state of a signal fall.
An operation of a conventional clock signal generation circuit is described with reference to a timing chart in FIG. 11.
First, using a reference clock signal 2101 from a reference clock signal generation circuit and a synchronization signal 2102, the number of edges of the reference clock signal 2101 in one cycle of the synchronization signal 2102 is counted in a counter circuit.
A count value 2103 is obtained by counting the number of edges of the reference clock signal 2101 and resetting a count value in accordance with the synchronization signal 2102.
A first clock signal 2104 and a second clock signal 2105 are two-phase clock signals generated on the basis of the count value. At this time, the duty ratio of the first clock signal 2104 to the second clock signal 2105 is 1:3. A period 2004 is a period when the first clock signal 2104 is in a high state (hereinafter, referred to as a “high period”), and a period 2005 is a period when the first clock signal 2104 is in a low state (hereinafter, referred to as a “low period”). Further, in the duty ratio of 1:3, a period which corresponds to “1” is the period 2004, and a period which corresponds to “3” is the period 2005. Although the duty ratio of each of the first clock signal 2104 and the second clock signal 2105 is 1:3 as described above, each low period has a different length in each cycle because an extra low period arises in dividing.
A control signal 2106 is generated on the basis of the first clock signal 2104 and the second clock signal 2105. When an initial state is a low state, the control signal 2106 is placed in a high state in accordance with a rise of the first clock signal 2104, and placed in a low state in accordance with a rise of the second clock signal 2105. At this time, in the control signal 2106 generated on the basis of the first clock signal 2104 and the second clock signal 2105, an N-th (N is a natural number) cycle is designated by 2009, and an (N+1)-th cycle is designated by 2010.
As shown in FIG. 11, the synchronization signal 2102 generated on the basis of the first clock signal 2104 and the second clock signal 2105 has different frequencies in the signal cycle 2009 and the signal cycle 2010. At this time, a low period 2007 in the signal cycle 2010 is 1.75 times longer than a low period 2006 in the signal cycle 2009.
As described above, a generated clock signal has a large difference in the length of low period in each cycle; therefore, it is difficult to perform a normal operation when a circuit is operated using a control signal generated on the basis of the clock signal.